-- psdiv_pkg.vhd (Pipelined signed non-restoring divider package) -- 'intersect' ray-triangle intersection soft core -- -- Copyright (C) 2007 Wenzel Jakob -- -- 01000000000000100000000 -- 00001000011111000001000 -- 00000001100000111000000 -- 01000010001110000101001 -- 00000110010001000100010 -- 00100110010011001100000 -- 10000100011000011000100 -- 00000110001111100000000 -- 00100011100000000010000 -- 00010000111111110000000 -- 00010000000000000001000 -- -- This program is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation; either version 2 -- of the License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software Foundation -- Inc. 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA library ieee; use ieee.std_logic_1164.all; package psdiv_pkg is component psdiv is generic ( -- Quotient, Divisor and Remainder width DATA_WIDTH : natural := 32 ); port ( -- Clock input clk : in std_ulogic; -- Dividend in 2s-complement z : in std_logic_vector(DATA_WIDTH*2-1 downto 0); -- Divisor in 2s-complement d : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Quotient output q : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Remainder = z - (d*q) s : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Indicates an overflow / division by zero ovf : out std_ulogic ); end component psdiv; component ppsdiv is generic ( -- Quotient, Divisor and Remainder width DATA_WIDTH : natural := 32; -- PIPE_DEPTH cycles of serial division are performed -- before the partial result is shifted into the next -- pipeline stage PIPE_DEPTH : natural := 4 ); port ( -- Clock input clk : in std_ulogic; -- Dividend in 2s-complement z : in std_logic_vector(DATA_WIDTH*2-1 downto 0); -- Divisor in 2s-complement d : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Quotient output q : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Remainder = z - (d*q) s : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Indicates an overflow / division by zero ovf : out std_ulogic; -- Indicates that values will propagate into and out -- of the divider on the next rising edge. prop : out std_ulogic ); end component ppsdiv; component ppfdiv is generic ( -- Quotient, Divisor and Remainder width DATA_WIDTH : natural := 32; -- PIPE_DEPTH cycles of serial division are performed -- before the partial result is shifted into the next -- pipeline stage PIPE_DEPTH : natural := 4; -- Fraction bits FRAC_BITS : natural := 16 ); port ( -- Clock input clk : in std_ulogic; -- Dividend in 2s-complement, fixed point z : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Divisor in 2s-complement, fixed point d : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Quotient output, fixed point q : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Remainder = z - (d*q) s : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Indicates an overflow / division by zero ovf : out std_ulogic; -- Indicates that values will propagate into and out -- of the divider on the next rising edge. prop : out std_ulogic ); end component ppfdiv; end psdiv_pkg;