-- intersect_pkg.vhd (Main intersect package) -- 'intersect' ray-triangle intersection soft core -- -- Copyright (C) 2007 Wenzel Jakob -- -- 01000000000000100000000 -- 00001000011111000001000 -- 00000001100000111000000 -- 01000010001110000101001 -- 00000110010001000100010 -- 00100110010011001100000 -- 10000100011000011000100 -- 00000110001111100000000 -- 00100011100000000010000 -- 00010000111111110000000 -- 00010000000000000001000 -- -- This program is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation; either version 2 -- of the License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software Foundation -- Inc. 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA library ieee, work; use ieee.std_logic_1164.all; use work.usb_iface_pkg.all; use work.fplib_pkg.all; use work.cache_pkg.all; package intersect_pkg is subtype memptr_t is std_logic_vector(22 downto 0); subtype triidx_t is std_logic_vector(21 downto 0); subtype reqid_t is natural range 0 to 65535; -- 16 bits component intersect_bd is generic ( -- Top 3 bytes of the version query reply ID_STRING : std_logic_vector(23 downto 0) := X"494E54"; -- Version query: FPGA major version MAJOR_VERSION : natural := 1; -- Version query: FPGA minor version MINOR_VERSION : natural := 1; -- Read/Write block size PACKET_SIZE : natural := 256 ); port ( -- Internal clock input clk0 : in std_ulogic; -- Global synchronous reset rst : in std_ulogic; -- USB / FIFO control inputs ctrl_i : out usb_ctrl_i_t; -- USB / FIFO control outputs ctrl_o : in usb_ctrl_o_t; -- DDR / Acknowledge flag ddr_ack : in std_ulogic; -- DDR Controller / Early acknowledge flag ddr_earlyAck : in std_ulogic; -- DDR Controller / Read acknowledge flag ddr_rdAck : in std_ulogic; -- DDR Controller / Operation input ddr_op : out std_logic_vector(1 downto 0); -- DDR Controller / Address input ddr_addr : out std_logic_vector(22 downto 0); -- DDR Controller / Data output (write) ddr_do : out std_logic_vector(31 downto 0); -- DDR Controller / Data input (read) ddr_di : in std_logic_vector(31 downto 0); -- Busy LED Output (unit 1) busy1_o : out std_ulogic; -- Busy LED Output (unit 2) busy2_o : out std_ulogic; -- Busy LED Output (unit 3) busy3_o : out std_ulogic; -- Cache busy LED Output cache_busy_o : out std_ulogic; -- OLED Controller / Write flag oled_wr : out std_ulogic; -- OLED Controller / Data input oled_do : out std_logic_vector(8 downto 0); -- OLED Controller / Acknowledge flag oled_ack : in std_ulogic ); end component intersect_bd; component intersect_main is port ( -- Internal clock input clk0 : in std_ulogic; -- Synchronous reset input rst : in std_ulogic; -- Data input flag data_i : in std_ulogic; -- Request id input reqid_i : in reqid_t; -- Data acknowledge flag data_ack_o : out std_ulogic; -- Is the unit ready for data? ready_o : out std_ulogic; -- Ray origin input ro_i : in fpval3; -- Ray direction input rd_i : in fpval3; -- Shadow ray input flag shadow_i : in std_ulogic; -- Cache control output cache_o : out rcache_i_t; -- Cache data input cache_i : in rcache_o_t; -- Calculation done flag; done_o : out std_ulogic; -- Distance travelled along the ray -- (overflow flag set if there is no intersection) t_o : out fpval; -- U coordinate output u_o : out fpval; -- V coordinate output v_o : out fpval; -- Shadow ray flag output shadow_o : out std_ulogic; -- Triangle index idx_o : out triidx_t; -- Request id output reqid_o : out reqid_t; -- Busy output busy_o : out std_ulogic; -- Clear performance counter input p_clear_i : in std_ulogic; -- Performance counter (full) p_full_o : out std_logic_vector(31 downto 0); -- Performance counter (empty) p_empty_o : out std_logic_vector(31 downto 0); -- Performance counter (cache hit) p_hit_o : out std_logic_vector(31 downto 0) ); end component intersect_main; component intersect_kd is generic ( -- 19 means no depth extension PIPELINE_LENGTH : natural := 19 ); port ( -- Internal clock input clk0 : in std_ulogic; -- Ray origin ro : in fpval3; -- Ray destination rd : in fpval3; -- Axis axis : in natural range 0 to 2; -- Split plane position split : in fpval; -- Bounds (near) mint : in fpval; -- Bounds (far) maxt : in fpval; -- Right node pointer left : in memptr_t; -- Right node pointer right : in memptr_t; -- Near node near_o : out memptr_t; -- Far node far_o : out memptr_t; -- Is the far node required? far_valid_o : out std_ulogic; -- Bounds (near) output mint_o : out fpval; -- Bounds (middle) output midt_o : out fpval; -- Bounds (far) output maxt_o : out fpval ); end component; component intersect_tri_insane is port ( -- Internal clock input clk : in std_ulogic; -- Ray origin ro : in fpval3; -- Ray direction rd : in fpval3; -- Range mint : in fpval; maxt : in fpval; -- Matrix coefficients a11 : in fpval; a12 : in fpval; a13 : in fpval; a14 : in fpval; a21 : in fpval; a22 : in fpval; a23 : in fpval; a24 : in fpval; a31 : in fpval; a32 : in fpval; a33 : in fpval; a34 : in fpval; -- U output u : out fpval; -- V output v : out fpval; -- T output t : out fpval; -- Valid hit output valid : out std_ulogic ); end component intersect_tri_insane; end intersect_pkg;